The invention pertains to a digital delay circuit.
More specifically, the present invention relates to a delay circuit for digital signals which are formed from a band-limited analog signal by means of an analog-to-digital converter clocked by a sampling signal of fixed frequency, and which are to be delayed by a selectable nonintegral multiple of the sampling period in a digital circuit system clocked by the sampling signal.
In digital circuit systems processing digital signals under control of a fixed-frequency clock signal, which may be identical with the clock signal of the analog-to-digital converter producing the digital signals from an analog signal, the shortest possible delay that can be realized by simple means is the sampling period. If, in such a system, delays shorter than the sampling period or nonintegral multiples thereof are to be generated, which is necessary, for example, when interpolating digital signals, the digital signals must be delayed by means of a delay circuit specifically designed for this purpose if it is impossible to increase the frequency of the clock signal so as to achieve shorter delays as a result of the shorter sampling period.